Ronald M. Martino
Vice President, Product Development and Hardware R&D
Freescale Automotive MCU Product Group
Wednesday, September 4, 2013
Title: "The Roadway to Innovation"
Ronald M. Martino is Vice President of Product Development and Hardware R&D for Freescale’s Automotive MCU Product Group. He is responsible for the development of Freescale’s Auto microcontrollers designs and product introductions. Responsibilities also include NVM process technology and IP module development. In addition, Ron is responsible for Freescale’s joint development partnership for automotive MCUs with ST Microelectronics. Prior to this, he was Vice Chairman of the Freescale Qiangxin IC Design Company based in Tianjin, China in addition to Vice President of Freescale’s worldwide microcontroller R&D organization responsible for development of both automotive and general market embedded processing solutions.
Ron joined Freescale in February 2008 from IBM, where he was director of Power Architecture offerings. He worked at IBM for 20 years with a focus on high-performance computing, networking, RF communication, and gaming microelectronics.
At IBM, Ron was Director of Power Architecture processor and licensing business focused on 32-bit and 64-bit MPUs from 2003 to 2008. Ron also served as Director of IBM’s ASIC and Core IP development organization, manager of IBM’s RF product introduction organization, and manager of an advanced technology support team from 1995 through 2002. Throughout this period, Ron also had assignments focused on strategic customer relationship management and gross margin enhancements. Prior to this, Ron held multiple engineering roles in advanced technology research and development.
Electronic innovation is becoming increasingly more important in the evolution of our society. Noble goals of extending healthy lives with improving medical capabilities, creating a cleaner environment, eliminating auto fatalities, and creating a connected infrastructure around the “Internet of Things” all center on electronic innovation. These goals are being driven by both legislation and consumer demand, which is leading to accelerated system challenges driving a strong need for integration of disparate functional blocks and exponential scaling of content.
A central focus in this evolution is the automobile. Emission standards are driving systems from single core, simple computational units to highly integrated, scaled out, safe and secure domain controllers, which host multiple diverse software environments. Shifts toward autonomous driving are leading to integrated sensing systems leveraging advanced algorithms for detection classification and safe decision making. The strong demand for connected vehicles is resulting in revolutionary changes to the vehicle network and communication infrastructure embedded in the automobile. We will explore how these automotive trends translate to future challenges for technology platforms, integrated circuit module development, system-on-chip integration, design of safe systems, and implementation of secure but diagnosable systems.
Product Marketing Director IP-Group
Cadence Design Systems Inc.
Wednesday, September 4, 2013
Title: “The pig in the poke? – Strategies to avoid unpleasant surprises with IP on your SoC”
Carsten Elgert is product marketing director for Cadence Design Systems, managing Cadence USB-, Flash- and Peripheral-IP product lines. Prior to Cadence he held various sales and marketing positions at Mentor Graphics for a total of 15 years before moving to Evatronix, where he served for 4 years as VP Sales and Marketing until its recent acquisition by Cadence. His career in the EDA industry started in application at Daisy Systems in 1983 and continued by moving via Caeco, Cadence to Intergraph Electronics (later Veribest), until it's acquisition by Mentor Graphics. Carsten holds an EE degree from the Technical University of Karlsruhe.
Developing an SoC and meeting the profitable market window just requires the intense use of pre-verified functional blocks, either “homegrown” or coming from external IP providers. The fast growing 3rd party IP market place is the direct consequence of this. While we can see significant changes in the kind of IP and its distribution models over time, the main concerns of an SoC designer remains the same: Will the IP work as anticipated, and how much time can I really save by using such a “Lego building brick” rather than developing the functionality from scratch? The talk will briefly compare the IP market and its maturity with the EDA market and address the change of requirements to IP over time. The trend towards next gen IP demands will be addressed. From this background the author will share important learnings to help users avoid the most common pitfalls when designing-in the IP into their next complex SoC.
Vice President of Business Development
Imagination, Inc., USA
Wednesday, September 4, 2013
Title: “Visions of future SoC Design: Why Heterogeneous Architectures and Power Matter”
Volker Politz is Vice President of Business Development at Imagination Technologies. He is an international business development and management executive with over 20 years’ experience in semiconductor and technology companies. Prior to his assignment at Imagination Technologies he has held roles and responsibilities in Europe, Asia and USA, with experiences built from engineering, marketing, sales and general management positions in Hitachi, Renesas and in his own consultancy company. He has broad know-how in vertical domains such as digital multimedia, broadcast technologies, automotive, industrial , mobile and security. Volker holds a Masters engineering degree in communication electronics from Fachhochschule Konstanz, Germany and an MBA from Open University, United Kingdom.
SoCs have transformed the semiconductor and electronics industries, integrating staggering breadth of functionality and performance into highly cost-effective, low power but complex single-chip solution platforms. However, total power consumption has been and is a challenge moving forward as SoCs keep increasing in performance and functionality whilst users shift from mains powered appliances to the use of battery driven equipment. The presentation therefore discusses some of these challenges and shows examples of how said challenges have been and will be addressed moving forward. Understanding technological and market trends and their drivers in key segments determine the ability to successfully translate vision into reality, and to constantly enhance it. The presentation further touches upon key functional blocks in modern SoCs and explains how the GPU is becoming the new driving force not only for modern applications but also for design methodologies and process technologies, and how heterogeneous processing is transforming the way SoCs handle key user applications such as UI’s, gaming, multimedia and more.
Prof. Dr.-Ing. Jürgen Herre
Chief Scientist, Audio/Multimedia Activities, Fraunhofer IIS,
Professor at University Erlangen-Nuernberg and International Audio Labs Erlangen
Wednesday Evening, September 4, 2013
Title: "The MP3 story and more: Perceptual Audio Coding from its Beginnings To the Present"
Jürgen Herre joined the Fraunhofer Institute for Integrated Circuits (IIS) in Erlangen, Germany, in 1989. Since then he has been involved in the development of perceptual coding algorithms for high quality audio, including the well-known ISO/MPEG-Audio Layer III coder (aka "MP3"). In 1995, Dr. Herre joined Bell Laboratories for a PostDoc term working on the development of MPEG-2 Advanced Audio Coding (AAC). By the end of 1996 he went back to Fraunhofer to work on the development of more advanced multimedia technology including MPEG-4, MPEG-7, and MPEG-D, currently as the Chief Scientist for the Audio/Multimedia activities at Fraunhofer IIS, Erlangen. In September 2011, he was appointed professor at the University of Erlangen and the International Audio Laboratories Erlangen.
Prof. Herre is a fellow of the Audio Engineering Society, co-chair of the AES Technical Committee on Coding of Audio Signals and vice chair of the AES Technical Council. He is a member of the IEEE Technical Committee on Audio and Acoustic Signal Processing, served as an associate editor of the IEEE Transactions on Speech and Audio Processing and is an active member of the MPEG audio subgroup.
mp3 and other audio coders have definitely changed the world of media production, distribution and consumption like few other technologies before. Perceptual audio coding is present on virtually every portable device, cell phone, PC and home or automative sound playback facility. How did it all start and what happended then? The talk will go back to the beginnings of the mp3 times, illustrate the next coder generations and finally talk about current challenges in audio coding & multimedia.
Thursday, September 5, 2013
Title: “Processor-to-Memory Interface Design Methodologies for Energy and Performance Efficiencies”
Bill Huffman is Chief Architect of Tensilica and has led the development and evolution of the highly flexible Xtensa archtiecture over the past eleven years. Before working at Tensilica, Bill was part of processor design teams at Computervision and Alliant Computer, and was Chief Scientist at Silicon Graphics, where he led the design of parts of the R-8000 processor and the Altix coherent memory supercomputer system. Bill holds S.B. and S.M. degrees in Physics from MIT and has been granted 32 patents.
Fundamental design goals for an SOC system including one or several processors often include lowest energy to accomplish the purpose of the chip, performance that meets the needs of the application, and reasonable hardware and software design effort to accomplish this. Often these don't track in the same direction. The effort to improve one of these may affect another dramatically. The talk will discuss the development process of different interface methodologies toward this end with particular reference to processor to memory interfaces and the movement of data from one processor to another. Examples of specific uses of Dataplane Processors with high bandwidth data movement in current systems will be discussed along with some novel methods of data movement between processors. In addition, other opportunities for reducing Energy and Time in the use of Dataplane Processors in low power systems will be considered.
Director Design Consulting
Thursday, September 5, 2013
Title: “Power-Centric Timing Optimization for Low Power CPU Hardening”
Jonathan Young joined Synopsys (Northern Europe) Limited in 2000 based in Reading, UK and is currently one of the world-wide leads for Physical Design within Synopsys Professional Services. Current responsibilities include defining SPS’ high performance core (CPU and GPU) strategy and managing the difficult transition to 16nm. Previous duties have involved the establishment, development and mentoring of SoC design centers across multiple geographies in Europe, India and Asia. Prior to Synopsys Jonathan has held various technical and application management positions at Sony Semiconductor and Texas Instruments. In the course of his 25 year career in SoC design and implementation Jonathan has been responsible for taking over 100 designs through tape out to silicon in technologies ranging from 3 um to 28 nm. Jonathan has a B.Eng (Hons) in Electrical and Electronic Engineering from the University of Reading, UK and is a Member of the Institution of Engineering and Technology, UK
Achieving the best performance, power and area (PPA) for processor cores is both a science and an art. A variety of interacting factors affect the achievable performance, power and area of a processor implemented in an SoC. In this session learn how to optimize the Quad-Core ARM® Cortex™-A7 MPCore™ processor for the best power efficiency targeted for entry mobile and other power-sensitive products.Shared best practices leverage Synopsys' high-performance core (HPC) methodology, including optimizations for power as a primary requirement to be managed at each step in the flow; from synthesis, placement, clock and routing, to post-route timing closure. Low power capabilities introduced here are augmented with aggressive power management of library VT classes and timing targets. The power-centric high-performance core methodology will be illustrated through a reference implementation of a quad core Cortex-A7 processor with ARM POP(TM) technology for core-hardening acceleration on TSMC 28HPM process. The final product is a strong starting point for designing the 'LITTLE' core in a big.LITTLE™ technology-based SoC, or as a stand-alone application processor for cost-sensitive markets.